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Eurotech BRI ISDN Manual de usuario Pagina 24

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Am186
TM
CC Microcontroller ISDN TA Reference Design Manual
2-6
The system uses a single 24-MHz crystal. This design uses an internal 2x PLL
which provides a 48-MHz system clock and the required 48-MHz USB clock.
Because the USB clock is derived from the system PLL, the USB crystal input,
USBX1, is terminated. The clock generation circuit is shown in Figure 2-3.
Figure 2-3. ISDN TA Clock Generation Circuit
X3
24.000 MHz
12
C57
27pF
C58
27pF
R33
10K
X1
X2
USBX1
about.book Page 6 Friday, December 18, 1998 9:41 AM
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